EDA Co-Simulation and Optimization of Structural Reliability for Full Lifecycle: Chip Design, Packaging, System Integration and Reliability Test

   Mr. Jian CHENG

   JCET Group, China 

Abstract:

This sharing will focus on EDA-driven full-lifecycle structural reliability co-simulation technology covering chip design, advanced packaging, system integration and physical reliability test verification, which closely aligns with the session's themes including Chiplet substrate optimization, closed-loop EDA workflow and industrial packaging manufacturing pain points mentioned in your email.

Speaker's Biography:

Cheng Jian, Expert Engineer and Lead of Structural Mechanical Simulation Platform in JCET Global Simulation Center. He received his Master degree in Chemical Process Machinery from Zhejiang University, and is currently pursuing his part-time doctoral degree at University of Electronic Science and Technology of China. He has rich R&D working experience in Fortune Global 500 enterprises . With 15 years of industrial experience, he focuses on multi-physics simulation and mechanics reliability of 2.5D/3D Chiplet packaging and system level products.