Trends in Bonding Technology Driven by the AI Era

    Dr. Haotian Tan

    Senior Marketing Strategy Specialist，Wisdom SemiTeC (Jiangsu) Technology Co.,Ltd.

Abstract: 

AI applications are driving the performance bottleneck of chips from process scaling toward interconnect delay and power consumption, positioning bonding technology as an increasingly definitive path in the post-Moore era. Currently, bonding technology has been volume manufactured in applications such as CMOS image sensor, 3D NAND, and Chiplet integration, while demonstrating significant potential across logic, memory, packaging, optical communications, and display applications. This presentation will provide a comprehensive overview of the latest advances in bonding technology application, covering both wafer-to-wafer and die-to-wafer bonding techniques, with a focus on emerging application scenarios. Furthermore, bonding technology still faces multifaceted long-term challenges. This presentation will summarize these technical challenges, review relevant fundamental research progress, and explore potential future solutions.

Speaker's Biography:

Dr. Haotian Tan received the Ph.D. degree in Microelectronics from Fudan University. He has published multiple journal papers and several national invention patents. With long-term experience in research on semiconductor processes, his work covers thin-film processes and devices, as well as advanced logic process integration. He currently serves as a Senior Marketing Strategy Specialist at WSTC, where his primary focus is on the application and research of advanced bonding technologies.