Challenges and Total Solution in Panel-level Fan-out Package
Dr. Yan HUO
SiPLP Microelectronics (Chongqing) CO.,LTD
Abstract:
Panel-level package is a new advanced fan-out technology that offers performance and cost advantages over wafer-level package. However, due to the early stage of development in the industry chain, there are numerous challenges and uncertainties in the mass deployment of panel level fan-out package, especially in terms of warpage control, die alignment, and product reliability, requiring continuous research and development efforts. SiPLP has introduced a ONEIRO fan-out package structure, utilizing its unique package processing technology to effectively address warpage and alignment issues in panel-level fan-out package. Additionally, based on the ONEIRO package technology, various package forms have been developed, including System in Package (SiP) design. ONEIRO fan-out package offers high reliability, low RDSON, high integration density, and excellent design flexibility, gaining widespread recognition and application in power semiconductors, industrial control, and RF switch fields.
Speaker's Biography:
PhD candidate at the University of Electronic Science and Technology of China, specializing in Integrated Circuit Engineering at Shanghai Jiao Tong University. Previously worked at AOS, Huawei and CR Micro, leading the development and mass production of various power semiconductor package technology platforms and semiconductor package equipment and materials development. Currently serving as the General Manager and R&D Director at SiPLP Microelectronics(Chongqing) CO.,LTD, leading the mass production introduction of advanced panel-level fan-out package technology. Filed 76 patent applications domestically (including Taiwan), with 69 inventions (35 granted) and 7 utility models. Also holds 8 granted foreign patents. Led the team to file over 300 patent applications.