Cu Paste for Bonding Applications in Advanced and Power Semiconductor Devices
Prof. Chuantong CHEN
Professor，Osaka University, Japan
Abstract:
Low-temperature copper (Cu) sinter-joining technology has attracted increasing attention in high-power electronic device packaging due to its low material cost and excellent electrical and thermal conductivity. Additionally, fine-pitch copper (Cu) pillar interconnects have been widely adopted in flip-chip packaging to enable high-density integration. In this talk, recent research on low-temperature Cu sinter-joining technology will be reviewed, including its background, development, challenges, and future perspectives in high-power electronics. Furthermore, its applications in advanced packaging will also be summarized.
Speaker Biography:
Chuan-Tong Chen，Full Professor, Joint Research Institute for 3D Electronic Packaging, Osaka University Senior Member of IEEE; Leader of Japan Wide Bandgap Semiconductor Industry Alliance; Kansai Regional Committee Member of Japan Institute of Electronics Packaging. He also serves as an international standardization committee member for Japan wide bandgap semiconductors, as well as a Technical Committee Member of IEEE ICEP, IEEE ICEPT, and the Power & Energy Technical Committee of IEEE EPS.
He has published more than 250 SCI/EI papers, holds over 20 Japanese and international patents plus 8 US patents, and co-authored 10 books. His accolades include the Best Paper Award from the Chinese Mechanical Engineering Society, the Japan Institute of Electronics Packaging Award, IEEE ICEP Outstanding Technical Paper Award, IEEE EMPC Best Poster Award, and the IEEE CPMT Japan Chapter Young Award, among many other honors.