High Speed Die-to-Die Interface and Chiplet System Design in Advanced Package

Dr. Yu WANG

Sr. Design Manager, KiwiMoore Semiconductor Co., Ltd.  

Abstract:

The rise of AIGC has escalated demand for computing capability, making it increasingly challenging for monolithic chip solutions to meet the requirements of high-performance chips. In response, the Chiplet approach delivers superior performance and efficiency while enhancing design flexibility and cost-effectiveness, thus increasingly emerging as a critical implementation for high-performance computing chips. Within Chiplet architectures, interconnects are among the most pivotal factors determining overall system performance and efficiency. Leveraging this novel chip architecture, die-to-die interconnects exhibit distinct characteristics that differ significantly from other interconnect paradigms.This report begins with advanced packaging for Chiplet solutions, introduces key features and emerging challenges of inter-die interconnects, analyzes technical trends in interconnect interfaces, discusses innovative solutions and process advancements, and provides design examples.

Speaker's Biography:

Dr. Yu Wang, Senior Design Manager at KiwiMoore Semiconductor Co., Ltd. He received the Ph.D degree from Fudan University. He has ten years of experience in semiconductor industry. His research interests are in high-speed interconnect interface IC designs. He has designed and delivered products featuring PCIe, UCIe, DDR, and other high-speed interfaces into mass production. He has published over 20 papers in top-tier IC design conferences and journals including ISSCC, JSSC, and TCAS. He holds over 10 patents.