x64 UCIe Chiplets at 32 GT/s on Emerging Silicon Core Substrate and Advanced TIM Cooling

Farhang Yazdani

CEO, BroadPak Corporation 

Abstract:

This keynote explores the design and implementation of a high-speed x64 UCIe chiplet interconnect operating at 32 GT/s on the emerging silicon core build-up substrate, addressing both signal integrity and thermal challenges. As bandwidth demands scale and chiplet architectures become mainstream, the integration of advanced substrates and thermal interface materials (TIMs) is critical to ensure performance, reliability, and manufacturability. The talk will highlight the co-design strategies used to achieve optimal electrical performance, the role of emerging silicon core build-up substrates in high-density interconnects, and the deployment of next-generation TIM solutions to manage heat dissipation in compact, high-power environments. Attendees will gain insight into the enabling technologies, integration trade-offs, and real-world implementation results that pave the way for scalable, high-performance chiplet systems.

Speaker's Biography:

Farhang Yazdani is the President and CEO of BroadPak Corporation, a leader in advanced 2.5D/3D heterogeneous chiplet integration and co-packaged optics design and manufacturing, based in San Jose, California. With more than two decades of experience across the global semiconductor industry, he has played a pivotal role in advancing system integration technologies through leadership positions in engineering, product development, corporate management, and strategic advisory roles.

He is the author of the book “Foundations of Heterogeneous Integration: An Industry-Based, 2.5D/3D Pathfinding and Co-Design Approach”, a widely referenced book that lays out a practical pathfinding and co-design methodology for 2.5D/3D integration. His work has earned him the 2013 NIPSIA Award for significant contributions to packaging innovation. He holds numerous publications and 40+ patents, serves on key technical committees, and frequently reviews for the IEEE Journal of Advanced Packaging.

He received his undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle.