Trends and Development Paths of Board-level Packaging

Dr. Kang ZHANG

R&D Director, Chengdu ECHINT Technology Co., Ltd.   

Abstract:

The adoption of 2.5D advanced packaging with interposers has become a necessary approach to meet the demands of artificial intelligence (AI) computing chips. Driven by the continuous pursuit of higher computing power, chip dimensions are steadily increasing, leading to increasingly prominent thermal mismatch issues. Consequently, the size of silicon interposers is approaching its manufacturing limit. Therefore, in the domain of large-scale chip packaging, the technological pathway is progressively shifting towards organic interposer solutions. However, constrained by limited wafer area, the availability of wafer-level packaging suitable for large-scale chips is restricted. Against this backdrop, panel-level packaging, leveraging its significant cost advantages, is emerging as a crucial alternative to wafer-level packaging.

Speaker's Biography:

Kang ZHANG, a doctoral in integrated circuits from the University of Electronic Science and Technology of China, is the R&D director of Chengdu Yicheng Technology Co., Ltd. He has been engaged in research on advanced Panellevel packaging technologies for a long time. Currently, he is mainly implementation of glass packaging and glass substrates.