Low-Temperature Solder Interconnection for Packaging

   Prof. Jusheng MA

   Professor, Tsinghua University, China      

Abstract: 

This lecture will examine the property optimization and performance enhancement of SnZn‑based low‑temperature solders, their behavior during reflow assembly, solder‑joint reliability and failure mechanisms, and the advantages these alloys offer for modern high‑performance packaging—along with future development prospects.

SnZn‑based low‑temperature lead‑free solders were developed to match the service characteristics of SnPb37 while providing an environmentally friendly alternative to SnAg3Cu0.5. Their key attributes include:

• Thermal properties comparable to SnPb37, enabling seamless use with existing equipment and low‑temperature devices originally designed for SnPb37 processes.

• Substantially improved solder‑joint reliability relative to SnPb37, including enhanced thermal‑fatigue resistance, oxidation resistance, and mechanical strength.

• Wettability superior to SnAg3Cu0.5 and on par with SnPb37, supporting robust joint formation across a wide range of metallizations.

• Higher joint strength and environmental reliability than SnAg3Cu0.5, making them suitable for advanced and reliability‑sensitive applications.

The discussion will also highlight the economic and manufacturing benefits of SnZn‑based alloys, such as reduced SMT reflow temperatures, lower power consumption, decreased material cost, improved reliability, and reduced thermal stress to high‑performance and large‑form‑factor packages.              

   Advanced System Packaging and Solder Interconnection

   Dr. Wei Koh

   Founder，Pacrim Technology Irvine, CA, USA

Abstract: 

Modern IC packaging for AI/HPC is rapidly evolving, with heterogeneous chiplet integration expanding beyond traditional System‑in‑Package (SiP) architectures toward large‑format system‑level integration modules—some reaching sizes of up to 125 mm × 125 mm.

This course will review several state‑of‑the‑art large system‑level integrated modules, including Nvidia’s CoWoP platforms, AMD’s SiP packaging progress, and Intel’s Panther Lake CPU module. The discussion will then examine the key integration components and enabling technologies, such as 2.5D silicon interposers, embedded bridging, and 3D TSV‑based HBM stacks, along with FOPLP glass panel processing.

The course concludes with an overview of emerging technology trends and the major challenges facing next‑generation system‑level module integration for AI/HPC.