Opportunities and Challenges of FOPLP and Electroplating Technologies for Advanced AI Chip Packaging

  Mr. Zhaowei Jia 

  Process Vice President，ACM Research (Shanghai), Inc.

Abstract: 

The surge in AI computing power has made advanced packaging a core driver of chip performance breakthroughs. FOPLP, with its panel-level integration and high cost-effectiveness, has emerged as a key solution for AI edge computing and other scenarios. Within this context, electroplating technology serves as the foundation for core processes such as RDL and micro-bumping. This presentation will focus on the synergistic development of FOPLP and electroplating, analyzing how electroplating enables high-density interconnection, cost reduction, and efficiency gains in FOPLP to meet the demands of AI chips.

Speaker's Biography: 

He graduated from Shanghai Jiao Tong University in 2007, majoring in Condensed Matter Physics. After that, he joined ACM Research and has been engaged in the development of semiconductor wet processing, electroplating and other related processes as well as equipment. Currently, he holds the position of Vice President of Process. Up to now, he has applied for more than 100 invention patents related to wafer electroplating technology, single-wafer megasonic cleaning, vapor phase etching technology, etc. As one of the core members, he has participated in the national major science and technology 02 Special Project, including the projects of "65-45nm Stress-Free Polishing Equipment and Process" and "45-14nm Electroplating Process and Equipment Development". He has obtained more than 100 authorized patents and published 4 papers. Received the First Prize of Shanghai Science and Technology Progress Award and the title of Pearl Engineer of Pudong New Area, among other honors.