Stress Sensing Test Chips for Application to Electronics Packaging

  Prof. Jeffrey C. Suhling

  Quina Professor and Department Chair, Department of Mechanical Engineering, and Center for Advanced Vehicle and Extreme Environment Electronics (CAVE3), Auburn University, IEEE Fellow,USA

Abstract: 

Test chips incorporating stress and temperature sensors are a powerful tool for characterizing the mechanical and thermal performances of a silicon die within an electronic package.  The on-chip sensors are semiconductor devices such as resistors, transistors, and diodes that are conveniently fabricated into the surface of the chip using microelectronic lithography processes.  With properly designed and calibrated sensor rosettes, the complete three-dimensional stress state and the temperature can be experimentally characterized at selected locations on the die surface using the measured changes in sensor electrical behavior (e.g., resistance changes and diode voltages) of the rosette elements.  Using specially designed test chips that incorporate an array of sensor rosettes, a full-field mapping of the stress and temperature distributions over the surface of a die can be obtained.  Thus, test chips can provide non-intrusive in situ measurements of stress and temperature deep within advanced electronic packages.  

In this talk, a review is made of the state-of-the-art for silicon test chips incorporating piezoresistive stress sensors and diode temperature sensors.  Developments in sensor theory, calibration methods, and rosette design for resistor stress sensors are presented.  In addition, enhanced sensor designs using FETs and van der Pauw structures are shown that enable sensor miniaturization and increased sensitivity.  Finally, several example applications of test chips to various electronic packages are illustrated including molded plastic packaging, flip chip assemblies, and advanced microprocessor packaging incorporating heterogeneous integration.  Case studies are presented where test chips have been used to identify and rank low stress encapsulants, detect and monitor underfill delamination progression, characterize moisture induced swelling, investigate transient microprocessor behavior during thermal cycling and power cycling, and measure compressive stresses in a microprocessor die during heat sink clamping.

Speaker's Biography: 

Jeffrey C. Suhling received his Ph.D. degree in Engineering Mechanics from the University of Wisconsin in 1985. He then joined the faculty of the Department of Mechanical Engineering at Auburn University, and currently holds the rank of Quina Distinguished Professor. He served as the Center Director for the NSF Center for Advanced Vehicle Electronics (CAVE) from 2002-2008, and as ME Department Chair from 2008-2025. His research concentrates on the mechanics, reliability, and materials science of electronic packaging and semiconductors; with emphasis on stress sensors and test chips, material characterization and constitutive modeling, and reliability testing and modeling. Dr. Suhling has co-authored over 600 technical publications on electronics packaging, with over 15,000 citations and an H-Index of 63 on Google Scholar.  He has advised over 100 graduate students at Auburn University including over 40 PhD students working in the electronics industry and academia. He is a Fellow of ASME, Senior Member of IEEE, and member of SMTA and IMAPS.  Dr. Suhling has been a member of the IEEE Electronics Packaging Society for the past 35 years, and is serving as Society President for a two-year term in 2026-2027.  He received the EPS William Chen Distinguished Service Award in 2024.