Chips Z: 2.5D/3D AI EDA+ Ushering in a New Era of STCO-Driven System-Level Collaboration for Advanced Packaging

  Dr. Alex Zhao

  Founder and Chief Scientist，Zhuhai Silicon Chip Technology Ltd. 

Abstract:  

In the post-Moore era, Chiplet integration based on 2.5D/3D stacking has shifted the design methodology from DTCO (Design-Technology Co-Optimization) to STCO (System-Technology Co-Optimization). Design requirements vary across heterogeneous and diverse scenarios, necessitating innovation in design tools, more complex solutions, and addressing issues such as inefficient iterations during design or difficulties in converging large-scale chiplet integrations.

SiliconCore Technology integrates its AI agent, Chips Z, into the dedicated 2.5D/3D EDA platform, 3Sheng Integration.

The self-developed 3Sheng Integration platform covers the entire back-end workflow, including architecture design, physical implementation, simulation and analysis, test and fault tolerance, and integration verification. Leveraging accumulated experience in advanced packaging design and process integration, the AI agent can perform requirement parsing, process matching, tool orchestration, automated optimization, system parameter tuning, and closed-loop design optimization. This addresses the limitations of traditional EDA tools, such as segmented workflows, poor collaboration, and frequent design callbacks. It is compatible with complex heterogeneous integration scenarios, including HPC, co-packaged optics, and microsystems-on-chip. By fusing AI with EDA technology, the platform effectively enhances automation and collaboration in advanced packaging design, providing robust technical support for engineering-level advanced packaging.

Speaker's Biography: 

Holding a Ph.D. from the University of Southampton, UK, under the supervision of Royal Society Fellow Professor Bashir Hashimi, he embarked on 2.5D/3D stacked IC design research in 2008 as part of one of the world's earliest pioneering research teams exploring advanced chip architecture methodologies, having collaborated with IMEC for 3D-IC technology validation. With 15 years of dedicated R&D in 3D integrated circuit design, he has published several excellent papers and awarded the VLSI-SOC Best Paper.