PROFESSIONAL DEVELOPMENT COURSE August 9th, 2023 10:00-19:00 Boxue Building, Shihezi University
PDC-1: Advanced Packaging Solutions for Advanced Node Chips

PDC-1: Advanced Packaging Solutions for Advanced Node Chips

Dr. Wei Koh, Pacrim Technology Irvine, CA, USA

Dr Koh has been working on IC packaging and microelectronics assembly technologies since the early 1980’s. He has MS and PhD degrees from Cornell University and worked for Henkel, Motorola, and Kingston Technology. As a Fellow of IEEE EPS, he has over 90 publications and 40 US patents relating to microelectronics.

Course Objective

IC Backend packaging, assembly, and test (PAT) has become a practical solution for continuing Moore’s Law in advancing the performance of small node semiconductors.  This course will review the evolution of IC packaging technology from conventional leadframe/BGA to wafer level 3D packaging to achieve heterogeneous integration and fine-pitch, high-density interconnections.  High density advanced packaging technology continues to evolve and moving forward using more complex design, new materials and high precision processes and metrology.  

This course is intended for the attendees to gain understanding on the fundamentals in IC packaging technology, applications, design, materials, and manufacturing processes that are progressing in high density advanced packaging (HDAP) technology to furthering the performance of sub 10 nm advanced nodes semiconductor ICs. Specific topic discussions are focus on heterogeneous and 3D integration for wafer level fan-out, fine pitch micro-bumping and hybrid bonding, chiplet interconnection, new packaging materials and thermal management for new generation advanced packaging.  Packaging examples for leading Fabs, IDMs, and OSATs are described.

Course Outline

·  Review of Conventional packaging technologies

·  Progress and Requirements in advanced node semiconductor, SOC and chip-let

·  High-end advanced wafer level fan-out technologies

·  Cu to Cu Hybrid bonding

·  Chiplet Interconnections

·  Thermal Management and Materials

·  HDAP Roadmap and packaging examples: TSMC, AMD, Intel, and Chinese OSATs

PDC-2: Achieving High Reliability of Lead-Free Solder Joints -- Materials Considerations

PDC-2: Achieving High Reliability of Lead-Free Solder Joints -- Materials Considerations

Dr. Ning-Cheng Lee, ShinePure Hi-Tech LTD

Ning-Cheng Lee is founder of ShinePure Hi-Tech. Prior to that, he was the Vice President of Technology of Indium Corporation. He has been with Indium from 1986 to 2021. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder materials for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies” by Newnes, and co-author of 5 other books. He received 1991 award from SMT Magazine and 1993 and 2001 awards for best proceedings papers of SMI or SMTA International Conferences, 2003 Lead Free Co-Operation Award from Soldertec, 2008 and 2014 awards from IPC for Honorable Mention Paper – USA Award of APEX conference, and 2010 Best Paper Award of SMTA China South Conference. He was honored as 2002 Member of Distinction from SMTA, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.

Course Description: 

This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions, and how those IMCs affect the reliability. The failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in detail. The selection of novel alloys with reduced fragility will be presented. Crucial parameters for high reliability solder alloy for automotive industry will be presented. Electromigration, and tin whisker growth will also be discussed. The emphasis of this course is placed on the understanding of how the numerous factors contribute to the failure modes, and how the selection of proper solder alloys and surface finishes for achieving high reliability are key. 

Course Outline: 

1. Mainstream lead-free soldering practices 

2. Surface finishes issues 

3. Mechanical properties

4. Intermetallic compounds 

5. Failure modes 

6. Reliability – Thermal cycle 

7. Reliability - Fragility

8. Reliability – Rigidity and ductility

9. Reliability – Composite Solder Enable Hierarchy Assembly & Shock Resistance 

10. Reliability – Tin whisker 

PDC-3: IEEE Heterogenous Integration Roadmap (HIR) Reliability Challenges and Roadmap

PDC-3: Chip to Package Interactions for Heterogeneous Integration Systems

Dr. Richard Rao,Senior Principal Engineer at Marvell Technology

Dr. Richard RAO is currently a Senior Principal Engineer at Marvell Technology and a Senior Member of IEEE.  Prior to joining Marvell, he was a Fellow of Microsemi (Microchip) Corp and a consultant engineer at Ericson Inc. His responsibilities include the development of design for reliability flows for advanced circuits, packaging, and chip to package interaction. He was the chair of IEEE EPS (Electronics Packaging Society) Reliability Technical Committee and co-chairing the reliability roadmap for the IEEE Heterogenous Integration Roadmap. He is also the general chair and technical program chair for the IEEE REPP (Reliability of Electronics and Photonics Packaging) Symposium.  He also serves as the technical committee chairs for the IEEE IRPS (International Reliability Physics Symposium). He has given many invited talks and keynote speeches to various international conferences. He has a Ph.D. degree in solid mechanics of materials from the University of Science and Technology of China and a post-doctor research fellow at Northwestern University studying the reliability failure mechanism of advanced integrated circuits. Prior to joining Marvell, Dr. Rao held senior technical positions in reliability physics and engineering for both academia and industries. He was an assistant/associate professor at University of Science and Technology of China and a research fellow for National Science and Technology Board of Singapore.


This tutorial examines the reliability implications of ‘SysMoore’, i.e. system-level heterogeneous integration (HI), that is being developed as a means to keep delivering the rate of performance increase, that we have come to expect because of Moore’s Law. Increasing system complexity, functionality, diversity, and density, as a result of the twin drives for HI and on-chip advances, will pose new challenges for meeting and verifying customers’ reliability targets. Multifunctional HI systems of the future are expected be complex multiscale and multiphysics systems. Heterogeneous integration requires a convergence between the semiconductor industry and the packaging industry, and a unified reliability approach across the entire product architecture hierarchy from device level to package, boards/ modules, and systems.  The resulting complex chip-package-board interactions (CPBI) will pose new reliability challenges and will need to be addressed by an integrated reliability team across all these levels of device-to-system integration, to meet the customer’s reliability targets. HI reliability engineers will also need to meet holistic constraints such as reducing the time required for new product introduction (NPI) and minimizing cost of ownership over the life-cycle of successive generations of products.  Such an integrated approach towards reliability will require a rigorous, disciplined, and proactive fusion approach that strategically combines a bottom-up reliability physics approach with a top-down approach that leverages powerful artificial intelligence algorithms and the unprecedented levels of real-time field performance data, service condition data, product stress data and system/component reliability data that is becoming available via IoT infrastructure. This tutorial lays out the scope, challenges, disruptive opportunities, and potential approaches for achieving such an integrated reliability approach for HI technologies, that are likely to emerge over the next 0-5, 5-10 and 10-15 years

This tutorial will focus on the following aspects of heterogenous integration reliability.

    1. Introduction of heterogenous integration packages such as chiplet, 2.5D and 3D package integrations for electronics and Silicon Photonics packaging.

    2. Reliability failure modes and degradation mechanisms for multi-level interconnects in the heterogenous integration system such as transistors, BEOL interconnects, TSV, uBumps, RDLs and hybrid bonding, etc.

    3. Chip to package interaction reliability challenges for advanced Si nodes

    4. Design for reliability

    5. Qualification for reliability

PDC-4: Computer aided processes and reliability for microelectronics and packaging interaction

PDC-4: Heterogeneous Integration: Tools, Design, Manufacturing, Infrastructure

Prof. Sheng LIU, Wuhan University, China

Prof. Sheng Liu is the dean of the School of Power and Mechanical Engineering and the Institute of Technological Science of Wuhan University. He is the National Science Fund for Distinguished Young Scholars (Type B), Yangtze River Scholar Distinguished Professor, ASME Fellow, IEEE Fellow, and as a professionalism in the area of the “863 program” of the National High Technology Research and Development Program. He has acquired his doctor degree in Stanford University in 1992. From 1992 to 1995, he held the title of lecturer at Florida institute of technology. He was authorized as a tenure from 1995 to 2001 in the Department of Mechanical Engineering and manufacturing research at Wayne State University. During the period of his title job, he was granted the President’s prize of USA. The research of IC and MEMS packaging with the research of CAD allowed him to obtain the Young Investigator Award in Natural Sciences of the United states of America. In 2001, Liu Sheng resigned from the Department of Mechanical Engineering and Manufacturing research at Wayne State University and returned to China, where he took the lead of carrying out research focusing on the theory of Reliable Engineering Development for LED electronic packaging.

PLENARY TALKS - August 10th, 10:00-19:45 North District Hall, Shihezi University
10:00-10:30 Opening Ceremony


10:30-11:00 Supply Chain Trends, Challenges, and Disruptions in Semiconductor Packaging

9:00-9:40 PLENARY TALKS1:

Dr. Kitty PEARSALL  President of IEEE EPS

Kitty Pearsall received the BS degree in Metallurgical Engineering and her MS and PhD degrees in Mechanical Engineering and Materials from the University of Texas. Across my 41-year career at IBM, I was appointed to strategic roles and received multiple awards.

Retired, IBM Distinguished Engineer in Integrated Supply Chain since 2000 - 2013

Emeritus Member of the IBM Academy of Technology 

Implemented global cross-brand, cross commodity processes/products 

Many IBM Outstanding Technical Achievement Awards; 12 US patents; and 8 published disclosures

Numerous internal IBM publications as well as 22 external publications

UT Austin – Cockrell Engineering Distinguished Engineering Graduate Award

UT Mechanical Engineering Dept. Academy of Distinguished Alumni

IBM Women in Technology Fran E. Allan Mentoring Award

Currently Kitty is President of Boss Precision Inc. and works as an independent consultant. Kitty has been an active member of IEEE for 31 years as well as an EPS member for 28 years, with growing roles and responsibilities, including ECTC Manufacturing Technology Committee, ECTC PDC Chair since 2006 and EPS/CPMT Board of Governors since 2005

11:00-11:35 Revolution of Microsystem Integration by lnnovations in High Performance Packaging

9:40-10:20 PLENARY TALK 2:

Mr. Li ZHENG  CEO of JCET Group Co., Ltd.

Mr. Zheng Li is a member of the board of directors and Chief Executive Officer at JCET Group Co., Ltd.  JCET Group is a leading global semiconductor system integration packaging and test provider, offering a full range of turnkey services that include semiconductor package integration design and characterization, R&D, wafer probe, wafer bumping, package assembly and final test. 

11:40-12:15 Surface Activated Bonding (SAB) for Low-Temperature 3D Integration

13:40-14:15  —  Surface Activated Bonding (SAB) for Low-Temperature 3D IntegrationProf. Tadatomo SUGA  Professor Emeritus of the University of Tokyo, Professor of Meisei University

Prof. Tadatomo Suga joined the Max-Planck Institut für Metallforschung in 1979, obtained his Ph.D. degree in materials science from University of Stuttgart in 1983. Since 1984 he has been a faculty member of the University of Tokyo and a professor in the Department of Precision Engineering of the School of Engineering since 1993. He was also the director of the Research Group of Interconnect Ecodesign at the National Institute of Materials Science (NIMS), a Member of the Japan Council of Science, and the Chair of IEEE CPMT Society Japan Chapter, as well as the President of the Japan Institute for Electronic Packaging (JIEP).

His research focus on microsystems integration and packaging and developing interconnect technology, especially the room temperature bonding technique for 3D integration. He has endeavored to establish collaboration between industries and academia for packaging technology, direct the R&D project of the Institute of Micro System Integration (IMSI), and also advocate the importance of the environmental aspects of packaging technology as the key organizer of the International Eco-design Conference.

In March 2019, he retired from the University of Tokyo and joined Meisei University to continue his research.

12:20-12:50 Tea Break & Networking


12:50-13:25 Metal Thin Film Equipment and Process Challenges in Advanced Packaging

13:45-14:15 Metal Thin Film Equipment and Process Challenges in Advanced Packaging

Bo GENG, Deputy General Manager of The PVD BU, Beijing NAURA Microelectronics Equipment Co., Ltd.


13:30-14:05 The Localization Trends and Challenges on Advanced Packaging Technology

15:50-16:20  —  The Localization Trends and Challenges on Advanced Packaging TechnologyMr. Cheng LI  Hygon Information Technology Co.Ltd

Graduated from Southeast University, majored in Electronic Engineering. Around 20 years’ experience in semiconductor industry, specially the expertise in Fairchild/AMD from discrete device to logic IC. Longly focus on 2.5D advanced packaging start from 2010 to develop engineering prototype with interposer technology, leading 2.5D testing & FA methodology initiatives. Leaded & covered CPU & GPU NPI work from post-silicon point of view with generations of leading edge process nodes experience. Recently put major efforts on localization for IC design & manufacturing related supply chain. Have integrated related supply chains from Mainland to assemble interposer 2.5D product & Fanout product, both comparable with abroad technology from package size & performance point of view. Continue the efforts to move to more localization areas including EDA & IP.

Speech Description: 

Advanced packaging technology is moving fast from both engineering & manufacturing sides in abroad, and recent years, the Domestic manufacturer is putting heavy efforts on this area as well with fast iteration. The late-development advantages from capital & talent sides will accelerate Domestic process development, and also the IC design house will have a better view on technology commercialization to screened out those with high-chance to success. This paper will focus on different methods to make a “2.5D” product from with both interposer & Fanout RDL efforts, we have co-worked & developed such product with local supply chains, all good to work. We will also focus on 3D, the challenge will even bigger, but from design house point of view, the challenge from product design、definition、post silicon logic is also giant, need to put all of these considerations systematically, we may then fully utilize the advance from advanced packading.



   1. Domestic Advanced Packaging Timeline Forecast

   2. Local 2.5D Packaging Choices & Discussion

   3. Challenges for Product Design & Production with Advanced Packaging

   4. Way for Advanced Packaging Localization & Summary

14:10-15:40 Lunch


15:40-16:10 Holistic ESD Protection Co-Design: Challenges

13:00-13:35  —  ESD protection design for integrated circuits and systems (including HI)

Prof. Albert Z Wang  Director, Center for Ubiquitous Communication by Light (UC-Light), University of California, Riverside

Albert Wang is a Professor of Electrical and Computer Engineering at University of California, Riverside, USA. His research covers semiconductor devices, analog/mixed-signal and RF ICs, design-for-reliability for ICs, 3D heterogeneous integration, emerging devices and circuits, and LED visible light communications. He published two books and 310+ peer-reviewed papers, and holds sixteen U.S. patents. His editorial board services include IEEE Transactions on Circuits and Systems I, IEEE Electron Device Letters, IEEE Transactions on Circuits and Systems II, IEEE Transactions on Electron Devices, IEEE Journal of Solid-State Circuits, and IEEE Transactions on Device and Materials Reliability. He has been IEEE Distinguished Lecturer for IEEE Electron Devices Society, IEEE Circuits and Systems Society and IEEE Solid-State Circuits Society. He was President of IEEE Electron Devices Society. He served as a Program Director of the National Science Foundation, USA. He was recipient of IEEE J. J. Ebers Award. Wang is a Fellow of National Academy of Inventors and an IEEE Fellow.

Speech Description:

Electrostatic discharge (ESD) protection has been a major reliability problem for integrated circuits (IC) and microelectronics systems, including bare dies and packaged microchips. Any on-chip/in-package/on-board ESD protection will inevitably affect system performance. On the other hand, 3D heterogeneous integration (HI) technologies and hetero-integrated microsystems lead to new complexity in ESD protection designs. Holistic ESD protection co-design hence becomes essential to advanced microsystem chips. This paper highlights key emerging ESD protection design challenges and discusses some ESD protection perspectives for future chips.

16:15-16:45 Manufacturing Technologies of Heterogeneous Integration for In-memory Computing

16:25-16:55  —  Manufacturing Technologies of Heterogeneous Integration for In-memory ComputingDr. Koukou Suu  Executive Officer and Senior Fellow, ULVAC, Inc. President & CEO, ULVAC Technologies Inc.

Dr. Koukou Suu graduated and received Ph.D degree in Engineering from Tohoku University, Japan in 1988 and 1993 respectively. He joined ULVAC, Inc. in 1993 and since then has been leading and engaging with developments of numerous semiconductor and electronics technologies including emerging non-volatile memories, high-K capacitors, LED, power devices, thin-film Li-battery as well as 3D packaging manufacturing technologies. He was General Manager of Institute of Semiconductor and Electronics Technologies of the company from 2008 to 2014. Currently he is Executive Officer and Senior Fellow of ULVAC, Inc. as well as President and CEO of ULVAC Technologies, Inc, a company representing ULVAC in North America. He is also an Adjunct Professor of Shanghai Institute of Microsystem and Information Technology of Chinese Academy of Science as well as an Adjunct Industrial Professor of University of South Australia. He has contributed to over 170 Patents (Japan, EU, US) and more than 80 industry & academic publications.

16:50-17:20 Hybrid bonding for next generation advanced interconnection technologies

17:00-17:30  —  Hybrid bonding for next generation advanced interconnection technologiesDr. Anton Alexeev  Business Development Manager of EV Group

Dr. Anton Alexeev is Business Development Manager at EV Group, where he focuses on wafer bonding technologies for a variety of 3D and heterogeneous integration applications.

 Anton received his PhD in electrical engineering from the Eindhoven University of Technology where he also graduated Professional Doctorate in Engineering program in physics. He has years of professional experience in the semiconductor industry. He worked on variety of technologies ranging from visible light communication via LED with Philips Lighting to optimization of the overlay performance for the leading-edge semiconductor manufacturing nodes with ASML.

Speech Description:

Hybrid wafer-to-wafer bonding gained over the past decade a significant interest as it can provide major advantages in fabrication of wafer-level interconnects. As an alternative process, die-to-wafer process flows were developed. Such approach is based on the principle of known good die: after wafer fabrication the dies are going through dicing and the dies passing the quality criteria are used to bond on a wafer. In this way, the bonding yield loss due to the individual wafers’ yield loss is minimized.

An overview of the two types of hybrid bonding will be presented. Two types of die-to-wafer process flows will be introduced. The main specifications and some of the main challenges of this technology will be reviewed with respect to their impact on process results. The importance of new metrology and investigation methods adoption will be emphasized.


Speech Outline: 

  ● Hybrid Bonding Introduction

  ● Die to wafer bonding process flows

  ● Substrates preparation

  ● Process results dependencies

  ● Metrology and process control

17:25-17:55 Tea Break & Networking


17:55-18:25 CPO Status and Technologies

18:05-18:35  —  CPO Status and TechnologiesMs. Yuan ZHANG  Senior Teacher

Yuan Zhang has worked in Huawei over twenty years, as an expert on advanced material and process R&D. In 2020, She left Huawei and has been engaged in part time training activities.

Speech Description: 

In this presentation, the concept understanding of CPO/NPO/LPO will be introduced. Then it will present the advantages of the potential products. In this talk, it will cover the CPO history, status and trends information from mainstream companies. And what key technologies including in CPO or NPO will be introduced too. At last, the speaker is going to analyze the supply chain challenges and relative standard work.



     1. The concept understanding of CPO/NPO/LPO

     2. The advantages of the potential products

     3. The CPO history, status and trends

     4. Tey technologies including in CPO or NPO

     5. The supply chain challenges and relative standard work

18:25-18:55 Paradigm Change of Design Rules from Electromigration to Thermomigration / Electromi

18:40-19:10  —  Paradigm Change of Design Rules from Electromigration to Thermomigration / ElectromiProf. Xuejun Fan  Lamar University, Beaumont, TX

Xuejun Fan is a Regents’ Professor of Texas State University System, and a Mary Ann and Lawrence E. Faust Endowed Professor at Lamar University, Beaumont, Texas. Dr. Fan is an IEEE Fellow, and an IEEE Distinguished Lecturer. He received the Outstanding Sustained Technical Contribution Award in 2017, and the Exceptional Technical Achievement Award in 2011 from Electronic Packaging Society of IEEE. Dr. Fan is a co-chair of Modeling and Simulation in Heterogeneous Integration Roadmap committee. 


As demand for high-performance semiconductors increases, heterogeneous integration using a combination of 3D monolithic and 2.5D/3D advanced packaging technology can boost the system performance significantly. Consequently, electromigation (EM)-induced failure in micro-bumps and redistribution lines (RDL) has become a great concern. In addition, thermomigration (TM) due to Joule heating, combined with EM, is becoming of the potential risks in future micro-/nano-electronics. In this presentation, I will present some general guidelines about design rules and accelerated tests for electromigration (EM)-induced failure, based on fully coupled modeling. For years, the existing EM theories have succeeded only in partially predicting or explaining complicated phenomena in experiments. Recently, we sorted out many incorrect models and assumptions under the framework of the coupling theory. In addition, taking multi-scale effects into consideration, we used molecular dynamics simulation to determine the key microscopic parameters, thus establishing a complete and self-consistent multi-physics coupling model of electromigration. We further conducted extensive EM tests and collected consistent test data for the purpose of model verification. The theoretical and numerical results fully reproduced the various phenomena in the experiments, including the impact of thermomigration. We then used the validated theory to provide new insights into design rules and acceleration factors to prevent EM-induced failure.

18:55-19:35 Advanced Packaging for Chiplet

17:00-17:30 PLENARY TALK 11:

Dr. Qidong WANG  Director of National Center of Advanced Packaging, IME-CAS

Dr. WANG Qidong received his B.S. degree in Electronics Engineering from Southeast University in Nanjing, MSc degree from Nottingham University in UK, Ph.D degree in Microelectronics and Solid-State Electronics from University of Chinese Academy of Sciences. He worked in Varian Lab, Stanford University as a Visiting Scholar from 2015 to 2016. He currently serves as the Director of Packaging and Integration R&D Center in the Institute of Microelectronics of the Chinese Academy of Sciences. 

20:00-22:00 Welcome Banquet


ORAL & POSTER SESSIONS August 11th(10:00-20:00)
Chiplets and Advanced Packaging for Future Computing and Communication

Chiplets and Advanced Packaging for Future Computing and Communicatio

Dr. Zhengda Wu Director of Samsung Electronics

Dr. Wu is currently working as Director of Business Development Team, AVP, Samsung Electronics. Prior to joining Samsung, he was CTO of Chengdu ESWIN System IC. He had also held several key positions in SJSemi and TSMC.  Wu received DPhil in Inorganic Chemistry from Oxford University, and MS & BS degree in Chemical Engineering from National Taiwan University & National Chung Hsing University, respectively.  Dr. Wu was granted several awards in recognition of his contribution in Advanced Packaging, including 2018 Jiangshu Innovative & Entrepreneurial Talent Award, 2019 Wuxi Taihu Talent Award, 2021 Chengdu Golden Panda Talent Program, and 2022 CSTIC Best Young Engineer Award from SEMICON China.  He has 14 journal and conference papers, with over 660 citations and H-index of 11. He also holds 40 US patents and 144 China patents on microelectronic packaging.

Speech Description:

With the ever-increasing demand for computing performance for mobile, IoT, AI, Big Data and automotive applications, the need for new solutions is growing due to the slowdown of Moore's Law and computing power solutions. Chiplets and advanced packaging are the key platforms to enable higher bandwidth and density for HPC and AI systems. This presentation will discuss how advanced packaging is enabling next generation computing and communication.

Embedded Silicon based Fan-out package with 2μm/2μm Line/Space multi-layer RDL

Embedded Silicon based Fan-out package with 2μm/2μm Line/Space multi-layer RDLProf. Wei WANG  Peking University

Prof. Wei Wang is the deputy dean of School of Integrated Circuits, Peking University and the director of the National Key Laboratory of Science and Technology on Micro/ Nano Fabrication. He received his B.S. in Thermal engineering from University of Shanghai for Science and Technology (USST, 1999) and the Ph.D. in Thermal Engineering from Tsinghua University (2005). He was a Visiting Professor in UC Davis (with Prof. Tingrui Pan) from 2007-2008 and Caltech (with Prof. YC Tai) from 2014-2015. His research focus is Parylene MEMS, clinical micro/nanosystem, and thermal management of 3D microsystem. He has published over 100 peer-reviewed articles, over 50 presentations with over 15 invited presentations, and 15 patents pending or granted. He is the Associated Editor of Microfluidics and Nanofluidics, Microsystems & Nanoengineering, and has served/ is serving on organizing committees for several international conferences, including IEEE MEMS’2015 and ‘2016, Transducers’2019, and 2021 etc.

Speech Description: 

Aiming at the demand for high-density interconnection in chiplet advanced packaging, the research on chiplet embedding reconfiguration wafer with sub-micron precision, low damage and high flatness of polymer flattening, and high-density silicon-based fan-out wiring process has been carried out. It solves the ultra-thin wafer (<50μm) low-stress thinning, high-precision (±2μm) lossless wafer cutting, chip embedding with sub-micron precision (<0.5μm), ultra-low porosity (<95%) high aspect ratio trench filling, ultra-low TTV (<1μm) reconstructed wafer surface polarization, and multi-layer high-density wiring problem. Finally, a multi-layer 2μm/2μm line-width/line-space silicon fan-out wiring technology was realized, which is expected to be applied to Chiplet advanced packaging technology.



    (1) Chiplet technology and application,the challenge of it’s packaging

    (2) Embedded silicon-based fan-out multilayer high-density wiring process

    (3) Summary 

Thermofisher solution for 3D packaging R&D and Failure analysis

Thermofisher solution for 3D packaging R&D and Failure analysisLinling Cai  Business Development Manager Thermo Fisher Scientific

Linling Cai is working for Thermo Fisher Scientific as PFA business development manager. She has more than ten years’ experience of customer application supporting work of PFA systems including the failure analysis in semiconductor industry. Being familiar with the theory and application of electron microscopy, she has supported many customer’s failure analysis cases for multifarious products including logic, memory, display, power device, packaging, and others. Based on her better understanding combining with the experience in application, she has provided various solution from EFA to PFA workflow to customers in different segments such as fabless, foundry, packaging house and others.

Speech Description: 

Advanced packaging complexity continues to grow because of requirement for thinner, smaller and more integrated IC products. This rising level of complexity introduces a wide range of integration challenges and associated defects. To identify the root cause of these defects, drive up yields and understand customer returns, more effective localization techniques are needed for failure analysis. Fortunately, Thermo Fisher has full FA workflow of EFA to PFA for advanced packaging. Lock-in Thermography (LIT) has been successfully demonstrated as a non-destructive analysis technique to locate the small defect. Furthermore, the high throughput FIB-SEM system can help find the defect under the surface and analyze the defects with high resolution by SEM and can provide 3D reconstruction precisely and efficiently. In this presentation, we will introduce our lock in thermography &dual-beam & SEM systems with case studies to failure analysis in advance packaging. 



the challenges in advance packaging / the whole solution from Thermo Fisher / production benefits and case sharing 

Development of Heterogeneous Integration Packaging Technology

Development of Heterogeneous Integration Packaging Technology

Dr. Daping Yao Chairman & CEO of Jiangsu CAS Microelectronics Integration Technology Co. Ltd

Dr. Daping Yao is the founder of Jiangsu CAS Microelectronics Integration Technology Co Ltd (Casmeit). Currently he serves as the Chairman of Board and General Manager for the company, which was established in March 2018 in Xuzhou city of Jiangsu province. After coming back from the US in June 2017, he joined the National Center for Advanced Packaging (NCAP) and had been responsible for various R&D projects of wafer level packaging technologies including TSV integration and FOWLP. He also bestowed a senior Principal Investigator of Jiangsu Industrial Technology Research Institute. Casmeit has been founded to be a high-volume production facility dedicated to advanced packaging. Over last a few years, the company has built the capabilities covering a variety of advanced packaging technologies, including wafer level high-density packaging, 3D system integration, system-in-package, and numerous other generic packaging technologies. Dr. Yao had worked for Applied Materials Inc California, USA for more than 20 years. His professional experience covers various areas including the development of semiconductor manufacturing processes, process integration, and equipment systems. Dr. Yao holds Ph. D. in Materials Science and Engineering from the University of Illinois at Urbana-Champaign, USA.

Speech Description:

It is well known that die or wafer stacking technologies are currently the main solutions that can meet the required performance of applications such as artificial intelligence (AI) and big data center. The most popular stacking integration technologies on the market are based on TSV interposer and TSV-less RDL interconnect for chiplets through heterogeneous integration. Currently, for example HBM and CIS are widely used through silicon via (TSV) technology. The recently emerged TSV-less technology consists of two groups: “with substrate” and “embedded in substrate”. Hybrid bonding can bridge the two main categories of “with TSV” and “without TSV”. This popular technique can be a complimentary or competition to TSV technology.

As building blocks to complicated heterogeneous packages, wafer level fanout technology and TSV interposer have enabled wafer level system-in-package, during which multiple dissimilar dies or systems can be integrated together. The fanout wafer level packaging balanced well the cost and performance for most high-end applications.



    1. Introduction to Heterogeneous Integration Packaging

    2. Building Components for an Integrated System

    3. Typical Characteristics of Heterogeneous Integrated Systems

    4. Summary

Chip to Package Interaction in Heterogeneous Integration Packages

Chip to Package Interaction in Heterogeneous Integration PackagesDr. Richard Rao,Senior Principal Engineer at Marvell Technology

Dr. Richard RAO is currently a Senior Principal Engineer at Marvell Technology and a Senior Member of IEEE.  Prior to joining Marvell, he was a Fellow of Microsemi (Microchip) Corp and a consultant engineer at Ericson Inc. His responsibilities include the development of design for reliability flows for advanced circuits, packaging, and chip to package interaction. He was the chair of IEEE EPS (Electronics Packaging Society) Reliability Technical Committee and co-chairing the reliability roadmap for the IEEE Heterogenous Integration Roadmap. He is also the general chair and technical program chair for the IEEE REPP (Reliability of Electronics and Photonics Packaging) Symposium.  He also serves as the technical committee chairs for the IEEE IRPS (International Reliability Physics Symposium). He has given many invited talks and keynote speeches to various international conferences. He has a Ph.D. degree in solid mechanics of materials from the University of Science and Technology of China and a post-doctor research fellow at Northwestern University studying the reliability failure mechanism of advanced integrated circuits. Prior to joining Marvell, Dr. Rao held senior technical positions in reliability physics and engineering for both academia and industries. He was an assistant/associate professor at University of Science and Technology of China and a research fellow for National Science and Technology Board of Singapore.

High Temperature Temporary Bonding/Debonding Materials (WLP TB5160/WLP LB601)

High Temperature Temporary Bonding/Debonding Materials (WLP TB5160/WLP LB601)Prof. Guoping ZHANG, Shenzhen Institute of Advanced Electronic Materials, Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences

Prof. Guoping Zhang received the Ph.D. degrees in applied chemistry from Hunan University, Changsha, China, in 2010, and went to the National Packaging Research Center (PRC) of Georgia Institute of Technology in 2014 for visiting scholar research. Prof. Zhang has been with the Shenzhen Institute of Advanced Technology (SIAT), Chinese Academy of Science (CAS), Shenzhen, China, since 2011. He is now the deputy director of Institute of Advanced Materials Science and Engineering, SIAT and the deputy director of Shenzhen Institute of Advanced Electronic Materials, SIEM. He has been a senior member of IEEE Society since 2023. He is mainly engaged in the research and application of advanced packaging materials for integrated circuits. He has undertaken and participated in more than 10 projects of National Natural Science Foundation of China, National Key R&D Program, Guangdong Provincial Science and Technology Innovation Team, Guangdong Provincial Key R&D Program, Shenzhen Science and Technology Program, and enterprise transversal, etc. He has published more than 100 SCI and EI papers, applied for more than 60 patents, obtained 20 authorized patents, 2 international PCT patents, and realized 5 patent transfers. In the transformation of scientific research achievements, he realized the transfer and transformation of patented technology and incubated the establishment of a high-end electronic packaging materials company.

Speech Description: 

As Moore's Law slows down, it is imperative to accelerate the deployment of advanced packaging technologies to meet the needs of high-end chips in terms of integration, multi-function and low cost. Shenzhen Institute of Advanced Electronic Materials is committed to the core technology breakthrough and technological innovation leadership of advanced electronic materials, and aims to build an internationally leading and 'irreplaceable' platform. With more than 10 years of R&D investment and technology accumulation, it can provide system solutions in key materials for advanced packaging of integrated circuits. In particular, the developed high-temperature-resistant temporary bonding materials by the research team have been widely used in advanced packaging fields such as wafer-level packaging, 2.5/3D packaging, and heterogeneous integration. This speech mainly introduces the high temperature resistant temporary bonding/debonding material (WLP TB5160/WLP LB601) recently developed by our research team. The material has the advantages of excellent corrosion resistance, temperature resistance up to 400°C, meeting the high productivity requirements of room temperature bonding, and compatibility with laser/mechanical debonding methods, and is suitable for high-temperature and high-stress applications in the semiconductor industry.



    1. High temperature resistant temporary bonding technology

    2. High temperature resistant temporary bonding materials

    3. Introduction of Electronic Materials Institute (SIEM)

    4. Introduction of the Samcien company

SCHOTT Glass Wafers and Circuit Boards - Enabling Advanced Packaging of Integrated Circuit

SCHOTT Glass Wafers and Circuit Boards - Enabling Advanced Packaging of Integrated Circuit

Dr. Ning DA, Sr. Operations Manager and Semiconductor Opportunity Leader in China SCHOTT Glass Technologies (Suzhou) Co., Ltd.

Dr.Ning Da graduated from the University of Erlangen-Nuremberg, Germany. He has nearly 20 years’ experience in the field of glass, glass ceramics and other brittle materials. He joined Schott Glass in 2013, and has been deeply involved in the technology research & development, and application of glass materials in the fields of consumer electronics and semiconductor industries. Currently, he is mainly responsible for the production and operation of SCHOTT glass wafers and related semiconductor technology products, as well as the promotion and application in the Chinese market. He has published more than 30 academic papers and applied for more than 10 PCT patents on glass materials and their applications.

Speech Description:

SCHOTT is a multinational high-tech company specializing in the field of special glass and glass-ceramics. With more than 130 years of material accumulation and technology development, we provide a wide range of high-quality products and solutions, and assist customers in many industries to achieve incessant success. SCHOTT is an innovation driver in many industries, such as semiconductor, medicine, household appliances, consumer electronics, optics, life sciences automotive and aviation. Especially, the glasses provided by SCHOTT are widely used in the fields of 3D imaging and sensing, MEMS and wafer level packaging, etc.

In the more than Moore era, with the development of the chiplet technology, the integrated circuit industry has put forward higher and higher requirements for chip types, quantities, high density, and integration. As an ancient material, glass is gradually favored by chiplet technologies for its excellent optical properties, stable chemical & thermal resistance, and customizable expansion coefficient & thickness. SCHOTT is continuously developing glass materials with various properties according to the needs of the global market, and fabricating glass wafers, carrier plates, or TGV of required specifications to meet the needs of current integrated circuit development. This speech mainly introduces that SCHOTT can offer large-scale mass-produced glass wafers and substrate materials with a wide range of thickness from 0.03 to 20mm or above. In addition, warpage, thickness tolerance, and TTV are all strictly controlled. Depending on the application, the glass wafers could be offered with various coefficient of thermal expansion (CTE) range from 3.2x10-6 to 9.4x10-6/ºC upon request. The speech also makes an in-depth explanation of the properties and performance of glass materials that affect the chiplet processes, so as to assist the development of chiplet industry.


Speech Outline:

    1. SCHOTT – Company overview

    2. Glass and Melting

    3. Schott glass wafers and panels

    4. Schott glass circuit 

Key Lithographic Materials Enabling High Density and Low-Loss Advanced

Key Lithographic Materials Enabling High Density and Low-Loss AdvancedMr. Zheng HAN, Senior Manager of JSR Electronic Materials (Shanghai) Co., Ltd.

He is a Sales Department Senior Manager in JSR Shanghai company. His current interest is to contribute to next generation advanced packaging for WLP/PLP and PCB industry. Today, he will present development status and roadmap of plating photoresist and photo-imageable dielectrics for advanced packaging. Furthermore, he will also introduce novel low Df polymer for PCB industry.

Course Description:

As advanced packaging technologies evolve, the importance of the redistribution layer (RDL) is growing. The RDL in an advanced packaging works not only for making bond pad location or expanding the interconnection area beyond die size, but also for connecting between dies with high density. Moreover, an advanced packaging requires a tall copper bump for making package on package (PoP) structure. We developed novel plating photoresists and dielectric materials for RDL and PoP that an advanced packaging requires. The photoresist (PR) shows excellent chemical resistance, good coating performance and great lithographic performance with high aspect ratio on sputtered copper. And our photo-imageable dielectric (PID) showed low residual stress, low shrinkage, low dielectric loss and great lithographic performance. Furthermore we have been developing novel low Df polymer for PCB industry in order to further contribute to the ever-evolving advanced packaging technology.


Course Outline:

    1. Introduction

    2. Plating Photoresists for Advanced Packaging

    3. Photo-Imageable Dielectric for Advanced Packaging

    4. Low Df polymer for PCB industry

Electro-thermal-Stress Collaborative Simulation Optimization for Key Technologies of 3D Integration

 Dr. Ziyu Liu Fudan University


A New Strategy of Cu/SiO2 Hybrid Bonding for Chiplet Integration

A New Strategy of Cu/SiO2 Hybrid Bonding for Chiplet IntegrationDr. Qian WANG Tsinghua University

Qian WANG received Ph. D in 2001 from Tsinghua University, china. Then started postdoctoral work at RCAST (Research Center for Advanced Science & Technology), the University of Tokyo and NIMS(National Institute for Materials Science) in Japan until 2003. From 2003.8, he joined Samsung and worked in SAIT (Samsung Advanced Institute of Technology) as a senior engineer. From 2006 to 2009, he went back to mainland China and worked in Samsung SSCR as a principle engineer and leader of Technology Development Group. Since 2010.3, he joined Institute of Microelectronics, Tsinghua University as an Associate Professor, his research focus on advanced packaging technologies such as SiP, MEMS Packaging, WLP 、3D integration、chiplet integration and  Heterogeneous Integration etc., Packaging reliability and failure analysis.

Keynote Abstract:

Hybrid bonding has been regarded as a critical ultra-high-density interconnect technology for Chiplet integration and data-intensive applications, such as data center, high-performance computing (HPC) and artificial intelligence (AI). In general, hybrid bonding can be realized by means of chip to chip (C2C), wafer to wafer (W2W) and chip to wafer (C2W) hybrid bonding. Considering of the throughout issue, C2C hybrid bonding will not be applied in high-volume manufacturing. Meanwhile, W2W hybrid bonding is limited because of the similar chip size and yield issues. C2W hybrid bonding can provide the flexibility for assembling variable chip sizes, thus it is suitable for chiplet integration and will be the mainstream. However, C2W hybrid bonding does introduce process complexity and face challenges such as particles and contaminants due to singulation, requirement of higher accuracy picking & placement, topography control of the Cu/dielectric surface, CMP process for metal recess and flat surface. Owing to the above rigorous process requirements, C2W hybrid bonding features a narrow process window and has a low bonding throughout.

To solve the aforementioned issues and reduce process time of C2W hybrid bonding and annealing for improvement of bonding throughout, we propose a new strategy of C2W hybrid bonding for chiplet integration, utilizing protruding Cu pads to achieve Cu/SiO2 hybrid bonding at the low temperature of 200℃ with the pressure of 30 MPa for a short bonding time of 5 mins. After every chiplet has been hybrid bonded to the wafer, the entire wafer is sent for annealing at the temperature of 200℃ for 30 mins. The bonding mechanism of conventional Cu/SiO2 hybrid bonding is that SiO2 is pre-bonded first and then Cu pads expand to bond and interconnect during post-bond annealing process. Compared with that, in this work, during the whole Cu/SiO2 hybrid bonding process, the protruding Cu pads will be connected first and flattened by temperature and pressure, which relaxes the stringent requirements of CMP and surface treatments, and also reduces post-bond anneal times and temperatures. Reduced time and temperature of bonding process contributes to improving throughout of C2W hybrid bonding. The bonding strategy illustrated here can provide a fresh understanding on low-temperature and fine-pitch C2W hybrid bonding for Chiplet integration.



Cu/SiO2 hybrid bonding; Low temperature; Chiplet Integration

Hybrid Bonding Technology in 3D Packaging

Hybrid Bonding Technology in 3D PackagingDr. Li GONG, General Manager of Suss MicroTec (Shanghai) LTD

Dr. L. Gong has studied material sciences at the university Erlangen - Nuernberg Germany. He has joint Fraunhofer Institute for Integrated Circiuts in Erlangen in 1987. His main research fields were semiconductor process technologies and measurement techniques. He has published over 20 scientific papers in magazines and international conferences. He has received the ph. D from the university Erlangen – Nuernberg. After many years teaching and research work, he joint Suss MicroTec in 1994. Since 2001 he is the general manager of Suss MicroTec (Shanghai) LTD. Dr. Gong is experienced in the field of semiconductor processes and equipment.



Advanced packaging tool technology and upgrading plan

Advanced packaging tool technology and upgrading planMr. Yun CHEN, Sales manager of ACM Research (Shanghai), Inc.

Yun Chen, with a bachelor’s degree, worked in CR Micro from 2014 to 2018. He was responsible for the debugging and optimization of front-end Track process. Since he joined ACM Shanghai in 2018, he has been responsible for the research and development and debugging of advanced packaging wet process tools, advanced packaging wet process and electroplating tools technical sales, etc., and is currently in charge of advanced packaging and third-generation semiconductor sales at ACM Shanghai. He has more than 8 years of semiconductor process and technical sales experience in the field of front-end process and advanced packaging.

Speech Description: 

With the ever-increasing chip stacking density and the demand for multi-chip integration, HDFO, 2.5D/3D and other more advanced wafer-level packaging technologies have been launched in China, and the requirements for related tools have continued to increase. ACM Shanghai has successfully solved the problems of warpage wafer handling and

Process. and successfully developed advanced single electroplating technologies/patents such as high-speed electroplating, special motion control stirring paddles, and six-element alloy elastic contacts. The electroplating deposition rate is well controlled at the same time as the electroplating uniformity, silver content and other parameters, effectively helping customers to increase production capacity while ensuring quality. In addition, ACM Shanghai also provides a complete set of advanced packaging wet-process solutions such as coating, developing, PR stripping, etching and cleaning.



The title is advanced packaging equipment technology and improvement plan. The main content is the process solutions of coating, developing, PR stripping, etching and cleaning tools in the field of packaging, the solution of warpage wafer handling and process of electroplating tools, and performance improvement of electroplating process, aiming to develop new application technologies based on market demand as a prospect.


 Zhong TIAN  University of Electronic Science and Technology of China

Robust Power Package Design with Simulation Driven Product Development

Robust Power Package Design with Simulation Driven Product DevelopmentDr. Haibo FAN Senior Principal Engineer of Nexperia Hong Kong

Dr. Haibo Fan, working as Senior Principal Engineer in Packaging R&D-Advanced Material Technology and Modeling, Nexperia Hong Kong. He got his PhD degree from Hong Kong University of Science and Technology (HKUST), then worked in HKUST, Philips LED lighting global R&D Center, NXP Hong Kong and Nexperia Hong Kong with 20+ year experience on simulation, and 15-year industry experience on design and reliability; He authored or co-authored more than 50 peer-reviewed technique publications, published 2 books and 3 book chapters.

Course Description:

 Simulation Driven Product Design and Development for Robust Power Package

 The design of power packages with both high efficiency and high-power density performance while maintaining the highest possible reliability is a challenge. However, there are a lot of reliability concerns, like delamination, die crack and solder crack etc. in power package, design optimization is needed to lower risk as possible. At same time, more strict requirement is addressed by customer to meet high requirements for application of automotive products. Therefore, a well understanding of factors causing these concerns can help drive design and process optimization for more robust package designs.

 Numerical modeling can play as a virtual prototype to predict the concern during assembly processes and extensive reliability testing for design and process optimization in automotive electronic, portable power electronics and high-power module. A simulation-driven design for manufacturing approach delivers manufacturability insights directly for early risk assessment to minimize some risks, like delamination, die crack, package crack, solder fatigue etc. for design and process optimization, helping bring products to the market as early as faster.

 In this talk, challenge in design and reliability from die level to board level will be discussed and several cases are demonstrated to show how designs are driven by simulation to achieve robust power package designs. Application of simulation AI-enabled simulation on semiconductor process and reliability will be discussed based on a methodology with a combination of machine learning and finite element analysis (FEA) as well.

Innovative Packaging Solution for SiC Power Device

Innovative Packaging Solution for SiC Power DeviceDr. Jing ZHANG Head of Shanghai Innovation Center, Heraeus Electronics China

Dr. Jing Zhang, head of Shanghai Innovation Center, Heraeus Electronics China, graduated from Delft University of Technology. His research of interests includes power electronic packaging material, process and reliability. In 2017, he joined Heraeus, focusing on advanced packaging and reliability evaluation for the WBG semiconductor devices. Dr. Zhang has led or participated in more than 30 domestic and international R&D projects worth more than 90 million RMB. He has also undertaken projects worth 40 million RMB as the first responsible person. Results of these projects have been transferred to many industries including new energy vehicles, high-speed rail and semiconductor lighting. He has published 20 papers, authored 1 book chapter and presented 9 reports as invited speaker at international academic conferences. Dr. Zhang is the Founding Chairman of IEEE Electronics Packaging Society (EPS) Benelux Branch, the Executive Secretary of the International Technology Roadmap for Wide Bandgap Power Semiconductors (ITRW), and a member of the Packaging Working Group. He also serves as a member of the Technical Committee of the Center for Shanghai Silicon Carbide POWER Devices Engineering & Technology Research, a member of the Youth Committee of the China Advanced Semiconductor Industry Innovation Alliance, a member of the Packaging Branch of the China Third Generation Semiconductor Roadmap Committee, and a member of the Nanotechnology Sintered Material Standardization Committee. He is an off-campus supervisor of master’s students at Fudan University.



Die Top System – A revolutionary solution for packaging and interconnection of SiC devices  As SiC power devices are increasingly used in many applications to enable higher power densities and switching frequencies, it becomes vital important to develop suitable packaging materials and solutions to maximize the benefit of such devices. One of the critical packaging processes is the interconnection of the upper die surface. However, traditional aluminum bonding wires are reaching their limits in terms of current carrying capability, thermal conductivity and reliability for SiC modules. Fortunately, copper wire bonding based on Heraeus Die Top System (DTS) creates robust interconnections and provides higher current capability and reliability. In this presentation, the DTS technology will be explored in details to show how and to what extent the solution can maximize the thermal, electrical performance and reliability of WBG devices.

Ag sinter joining and beyond Ag sinter joining technologies for WEB power device in high temperature

Ag sinter joining and beyond Ag sinter joining technologies for WEB power device in high temperatureProf. Chuantong CHEN  Osaka University

Chuantong Chen, received the master's degree and Ph.D degree in mechanical engineering from Nagoya Institute of Technology, Japan, in 2012 and 2015, separately. From 2016 to 2019, he was an assistant professor at Institute Scientific and Industrial Research, Osaka University, Japan. He became to an associate professor in Osaka University from 2020. His research interest includes lead-free soldering, Ag sinter joining, Nano-joining, 3D packaging, and power electronics packaging. Prof. Chen was a recipient of some awards and honors including the IEEE ICEP Outstanding Technical paper Award in 2023, and the IEEE CPMT Japan Chapter Young in 2019. He has published including IEEE T Power Electr, Acta Mater, Scripta Mater, Appl Phys Lett, more than 100 journal papers and about 70 conference papers in above fields. He also applied and obtained 15 Japanese and international patents, including 3 US patents. Prof. Chen serves as technology committee member of IEEE ICEPT from 2020, and serves as the committee member of Kansai branch of the Japanese Electronics Packaging Society from 2020, and also a committee member of International standardization for the third-generation semiconductor packaging substrate material, interconnections, heat conduction evaluation system and equipment in Japan from 2018.

Speech Description: 

SiC and GaN have a wider band gap than Si, and they are able to withstand both high-temperature and high-frequency operation. The SiC and GaN can reduce power loss and overall downsize the power electrical equipment. Operation temperature of SiC power modules may achieve above 250℃ due to higher power application. Silver (Ag) sinter joining is becoming an important interconnection technology for die attach in power electronics. It exhibits superior process ability, high-temperature resistance and long-time durability to traditional connection methods such as solder joining or conductive adhesive joining. Massive works have demonstrated Ag sinter paste is capable to achieve a robust and reliable die attach on DBC substrate under a mild sintering condition (pressure-less, low temperature and atmospheric sintering). However, Ag sinter joining is also facing some huge issues, for example, high price especially for the Nano-Ag paste, excessive interfacial stress and reliability problems caused by the large mismatch of CTE (thermal expansion coefficient) between SiC, and the problem of coarsening of microstructure of sintered Ag paste caused by thermal migration during high temperature. In this presentation, we will summary the Ag sinter joining and propose some new die attach technologies to achieve for the low material cost and high reliability in high temperature of SiC power modules.

Die attach technologies such as Cu sinter joining, Ag-Si composite sintering, and Ag-Cu composite sintering will be introduced for the high temperature application with a properties of low-cost, low-CTE and high reliability.

The bonding quality and bonding mechanism will be also introduced for a comprehensive understanding of SiC power modules beyond Ag sinter joining.



    a. The background of SiC power modules and required die attach materials

    b. Ag sinter joining technology and its reliability issues

    c. Development of Cu sinter joining technology and apply for SiC power modules

    d. Emerging Cu-Ag sinter joining technology for bare Cu in air condition sintering

    e. Low-cost low-CTE and high reliability Ag-Si composite paste 

Fault detection and protection technology for AC/DC hybrid power grid with high proportion of renewa

Fault detection and protection technology for AC/DC hybrid power grid with high proportion of renewaProf. Bin WANG Tsinghua University

Dr. Bin Wang, he is associate professor of the Department of Electrical Engineering of Tsinghua University, doctoral supervisor, IET Fellow, distinguished professor of oasis scholars of Shihezi University, deputy director of Beijing International Science and Technology Cooperation Center for Green Energy and Power Security, and vice chairman and secretary-general of IEEE China Satellite Substation Committee.  He has been engaged in teaching and research in the fields of fault analysis and safety defense for AC/DC hybrid power grids, as well as health diagnosis and causal analysis for power grids based on artificial intelligence.  He completed 18 key projects such as the China Association for Science and Technology International Science and Technology Organization Affairs Special Project and the Natural Science Foundation of China as PI, and won the second prize of the 2017 National Technology Invention Award and 8 provincial and ministerial level first prizes in Beijing City, Shaanxi Prov., Jilin Prov., Fujian Prov., and China Electric Power Science and Technology Awards.

Speech Description:

Introduce the security requirements and technical challenges of the AC/DC hybrid power grid carrying a high proportion of renewable power generation. From the two levels of transmission network and distribution network, the relevant key technologies such as fault analysis, fault detection, relay protection, fault location, Artificial Intelligence for IT Operations are introduced.

Characterizations of 1700V Silicon Carbide Power Modules in Planar Packaging Based on Domestic Chips

Characterizations of 1700V Silicon Carbide Power Modules in Planar Packaging Based on Domestic ChipsProf. Yunhui MEI Tiangong University

Yunhui Mei, Professor, Executive Vice President of School of Electrical Engineering, Tiangong University. He has been engaged in the research of power electronic device packaging and reliability for a long time. In recent years, he has presided nearly 30 projects. He is serving as a director of the China Power Supply Society, deputy director of the Component Committee, IEEE Senior Member, editorial board member of the Journal of Power Supply, and deputy chairman of the Tianjin Power Supply Society. He has published over 140 academic papers, including 97 SCI papers and 27 granted invention patents. I have won the IEEE CPMT Young Award, the First Prize of the Technology Invention Award of the China Power Supply Society, the First Prize of the Technology Invention Award of the China Electrical Engineering Society, and the First Prize of the Tianjin Technology Invention Award, Henry Fok Education Fund of the Ministry of Education, Science and Technology Award for Youth in Colleges and Universities, IEEE International Power Electronics Annual Conference APEC Best Presentation Award, National Third Generation Semiconductor industry Technology Innovation Strategic Alliance (CASA) 'Special Contribution Award', etc.

 Automotive Electronic Packaging and Its Future Development

 Scott CHEN  SVP of Central Development Engineering in ASE (Advanced Semiconductor Engineering)

Scott received B.S. degree in Chemical Engineering from NTU (National Taiwan University). And Master degree of Executive MBA Program from NTU. He has been worked on each of assy technology , MEMS nsor, bumping, flip chip , advance package technology and SIP solution over 30 yrs. 

Development of high reflectance insulating film materials for packaging semiconductor optical device

Development of high reflectance insulating film materials for packaging semiconductor optical deviceDr. Chen Wei-Su  Deputy General Manager of Quantech (Guangzhou) New Materials Co., LTD

About the personal work profile of Dr. Chen Wei-Su in Quantech (Guangzhou) New Materials Co., LTD : Dr. Chen worked as an equipment engineer in Taiwan Industrial Technology Research Institute of from 1997/10/1 to 2002/10/1 and was responsible for the maintenance of semiconductor logic integrated circuit equipment. 2002/11/1-2003/10/1 Served as Technical Manager of Taiwan RiTDisplay Technology Co., LTD responsible for red and blue OLED components. 2003/11/1-2017/10/1 Served as Supervisor and Manager of R&D Department of Taiwan Industrial Technology Research Institute, responsible for the construction of relevant 300mm process for applications of new-Non-Volatile Memories. 2017/11/1-2019/10/1 Worked in PSK Co., LTD. (Korea), responsible for the process construction and verification of post-production dry photoresist stripping machine. 2019/11/1-2020/10/1 Served as a Chair Professor in the Railway Power Supply and Electrical Department of Shandong Polytechnic College, responsible for electronic technology teaching and semiconductor related courses. 2020/10/1 Served as Deputy General Manager of Quantech (Guangzhou) New Materials Co., LTD in Guangzhou headquarters of the company, responsible for the establishment of high-end electronic spin-coating chemical material class 10&100 clean room factory and the project development of mass production products. 

Speech Description:

The high reflectance insulating layer protective film used in semiconductor or display optical devices is made of Bragg Reflection structures formed by repeated overlapping coating of high index metal-containing and low index silicon-containing insulating layers. In this paper, the manufacturing process, baking process, optimization of surfactant formulation of ultralow refractive index Spin-on Glass (SOG) encapsulation insulating layer material, the effect of aging in air on coating defects, and the effect of filtering SOG solution for fine dust on film surface are reported. The minimum refractive index (n) of SOG reported in this paper can be lower than 1.2@633nm wavelength, and the optimum baking process is three steps of low, middle and high temperature baking 80℃/150℃/300℃, respectively. The optimal material weight ratio of surfactant is 1 basic unit. Isolation of water and/or oxygen in the air can eliminate spin coating defects. The fine dust on the film surface is eliminated after filtrating the liquid. At present, the SPC data of this material has reached the mass production specification.



1. Introduce the application of Ultralow-RI SOG, 2. Ultralow-RI SOG manufacturing procedure, 3. Ultralow-RI SOG baking and curing procedure, 4. Ultralow-RI SOG surfactant optimization formulation, 5. Effect of aging of liquid medicine on Ultralow-RI SOG dust and spin coating defects, 6. The effect of liquid filtration on the reduction of fine dust.

Development of Integrated Passive Devices Based on Glass Substrate and TGV Process

Development of Integrated Passive Devices Based on Glass Substrate and TGV ProcessDr. Wenbiao RUAN R&D director of Ximen Sky Semiconductor Technology Co. Ltd.

Ph.D, majoring in Electronics and Solid State Electronics at the Chinese Academy of Sciences, currently serving as the Director of R&D at Xiamen Yuntian Semiconductor Technology Co., Ltd., responsible for the research and development of processes such as through glass via (TGV), fanout packaging (WL-FO), wafer level packaging technology, and glass based high-frequency devices. He has successively served in SMIC., Institute of Microelectronics and Detection Technology. In 2010, he was appointed as an associate researcher at the Institute of Microelectronics, conducting research on the modeling of integrated circuit manufacturing processes and manufacturability design methodology for 65 nm and below node, and participating in and completing multiple national major special research projects. Published over 10 articles and applied for 18 patents.

Speech Description: 

IPD (Integrated Passive Devices), which applies mature and advanced integrated circuit manufacturing processes, has the following advantages compared to traditional passive devices: significantly reduced volume, lighter weight, higher performance, and better consistency, making it an effective solution for miniaturization and high integration requirements of RF systems. Based on glass substrates, Yuntian has successfully developed TGV manufacturing technology, reaching international advanced levels. It has researched high aspect ratio TGV filling technology and the ability to design and implement multi-layer RDL wiring. On this basis, it has closely cooperated and collaborated with IPD design enterprises to develop high-performance passive components such as inductors, capacitors, filters, millimeter wave antennas, etc., laying the technical foundation for achieving high-density and miniaturized high-frequency integrated systems.



    1. IPD requirements

    2. TGV process capability

    3. IPD devices based on glass substrate

    4. Summary

Low-temperature solid-state bonding for chip interconnection

Low-temperature solid-state bonding for chip interconnectionProf. Hongjun JI Harbin Institute of Technology, Shenzhen

Hongjun Ji, studied at Harbin Institute of Technology from 1999 to 2008, received his Ph. D. in engineering and is currently a professor in the School of Materials Science and Engineering at Harbin Institute of Technology (Shenzhen). He has long been engaged in the basic and applied basic research of power ultrasound in the fields of micro-nano joining and advanced interconnection in electronic packaging. His main research interests include ultrasonic processing principles and technologies (ultrasonic assisted synthesis of materials, ultrasonic metal welding, ultrasonic assisted plastic deformation, and microstructure and properties evolution under ultrasonic excitation, etc.), and advanced electronic packaging interconnect materials and micro-nano joining technologies (wire bonding, and chip bonding, etc.). More than 70 SCI papers have been published in international high-level professional journals, such as Scripta Materialia, Ultrasonics Sonochemistry, and more than 50 papers have been published in international conferences. Furthermore, he has been invited to deliver oral presentations at ECTC, ICEPT and other international conferences on electronic packaging more than 40 times.

Speech Description:

Chip interconnection with low process requirements, high interconnection quality, and excellent stability is preferred in advanced packages characterized by high thermal/electrical conductivity, low temperature bonding and high reliability. Low-temperature Cu-Cu bonding technology is the key technology of future advanced packaging technology. Compared with the Sn-based soldering process currently used, low-temperature Cu-Cu bonding technology provides fine pitch interconnection, excellent electrical and thermal conductivity, and better reliability. Based on the background of low-temperature chip interconnection in advanced packaging, this oral presentation will introduce the latest research progress of low-temperature Cu-Cu bonding for advanced packaging interconnection applications. Combined with the research results of our research group, the Cu-Cu ultrasonic welding process and low-temperature Cu-Cu bonding technology using nanomaterial interlayer, and low-temperature Ag-Ag bonding technology will be introduced.



    1. Requirements and challenge of low-temperature chip interconnection. 

    2. Low-temperature Cu-Cu bonding technology. 

    3. Low-temperature Ag-Ag bonding technology.