Advanced System Packaging and Solder Interconnection

Dr. Wei Koh

Pacrim Technology Irvine, CA, USA

Abstract: 

Modern IC packaging for AI/HPC is rapidly evolving, with heterogeneous chiplet integration expanding beyond traditional System‑in‑Package (SiP) architectures toward large‑format system‑level integration modules—some reaching sizes of up to 125 mm × 125 mm.

This course will review several state‑of‑the‑art large system‑level integrated modules, including Nvidia’s CoWoP platforms, AMD’s SiP packaging progress, and Intel’s Panther Lake CPU module. The discussion will then examine the key integration components and enabling technologies, such as 2.5D silicon interposers, embedded bridging, and 3D TSV‑based HBM stacks, along with FOPLP glass panel processing.

The course concludes with an overview of emerging technology trends and the major challenges facing next‑generation system‑level module integration for AI/HPC.

Outline:

Lecturer Biography: