EDA Co-Simulation and Optimization for Structural Reliability Across the Full Chip Lifecycle: Chip Design, Packaging, System Integration, and Reliability Verification

   Mr. Jian Cheng

   Expert Engineer, JCET， China 

Abstract:

This presentation focuses on EDA-driven co-simulation technologies for structural reliability throughout the entire chip lifecycle, covering the full development workflow from chip design and advanced packaging to system assembly and product reliability testing and verification. Closely aligned with the theme of this session, the talk will explore chip and system design optimization, closed-loop EDA design flows, as well as key pain points and engineering challenges in industrial-scale packaging manufacturing. The goal is to provide systematic methodologies and practical references for structural reliability design and verification of advanced packaged products.

Speaker's Biography:

Cheng Jian is an Expert Engineer in the Technology Service Department at JCET and the lead of the Structural Mechanics Testing and Simulation Platform. He holds a Master's degree in Chemical Process Machinery from Zhejiang University and is currently pursuing a part-time Ph.D. at the University of Electronic Science and Technology of China. He has long been engaged in research on the mechanical reliability of advanced chip packaging and systems. With 15 years of industrial R&D experience, he has published multiple papers as first/corresponding author at the top international packaging conferences including ECTC and ICPT, and holds multiple granted patents in China and abroad.