|
Professional Development Course (PDC)
To register for PDC, please go to "Conference Registration"
Introduction of instructors and courses
1. Advanced Failure Analysis of Semiconductor Packaging
Key FA tools were developed with Semiconductor growth. It is an essential part of the semiconductor technology, as the physical failure root cause and mechanism finding is the key for break through the barrier in technology innovation. Every break-through of FA tool or technique brings forward the semiconductor development. It enables continuously business growth.
The goal for this short course is to address the state-of-the-art of semiconductor failure analysis from various aspects:
1. 60 years history of FA tools and FA role in industry
2. Advanced FA tools and FA techniques
3. Broad cross-field transfer know-how in modern FA
4. Future challenges and Roadmap
The course will be divided into three main sections:
1. The first section would discuss the FA tools history development and its role for semiconductor development. The fundamental driver for FA would be discussed.
2. The second section would elaborate the advanced FA based on the latest practical cases from chip level, package level to PCBA level.
3. The third section would review on the new challenges and the latest semiconductor FA roadmap.
Course Outline:
1. The 60 years development of failure analysis
2. The role of failure analysis
3. Advanced FA tools and techniques
A. Electrical verification and fault localization
B. Preparation (Chip level, and packages)
C. Imaging and material characterization
4. Cross-field transfer know-how in practicing modern failure analysis
A. Practical cases study (DSO, QFP, VQFN, Stack-die, BGA, Flip-chip, Sip, WLB)
B. Package reliability risk characterization
5. Semiconductor Failure Analysis Roadmap
A. Technology trend
B. Drivers
C. Challenges for FA
Biographies of Instructors:
2. High Density Interconnect and Substrate Technologies for System-in-Package
This course will introduce the cutting-edge information on the most important development and latest research results in applying high density interconnect and substrate technologies to advanced packaging. For professionals active in microelectronic packaging research and development, those who wish to master high density interconnect and substrate technologies, and those who need to choose a cost-effective design and high-yield manufacturing process for their electronic systems, this is a timely summary of progress in all aspects of this technical field. The lecture contents are based on the instructor's books on electronic packaging, his recent research results, and interactions with the packaging and assembly industries. The scope of course covers system-in-package technologies, high density routing, through silicon vias, microvias and build-up layers, silicon interposers and organic substrates, coreless substrates, and special high density interconnect technologies. With the information provided in this lecture, the attendees will acquire a practical understanding in the design, materials, processes, analysis, and reliability issues of high density interconnect and substrate technologies for system-in-package.
Course Outline
1. Overview of system-in-package technologies
2. Area array interconnection and high density routing
3. Through silicon vias and silicon interposer
4. Microvias and build-up layers
5. Coreless substrates
6. Special high density interconnect technologies
7. Applications and case study
8. Outlook for technology roadmap
Biography of Instructor:
3. Advanced Cu Wirebonding Technology
Wire bonding is the most dominant form of first-level chip interconnects in microelectronics with gold wire bonding taking the lead for the past few decades. Today, it is evident that the shift from gold to copper wire bonding is genuinely picking up, due to both surge in gold price and recent development in copper wire bonding technology.
The goal for this short course is to address the maturity of copper wire bonding from various aspects:
1. The technology trends and is it sustainable for the industry to adopt copper wire bonding in replacing gold wire bonding and if so, will gold wire bonding be phasing out.
2. How do the recent development in equipment, copper wire and capillary help realize copper wire bonding in production implementation.
3. What are the key process factors to achieve a reliable copper wire bond.
4. What are the implementation challenges with the downstream process such as interaction with mold compound and its package reliability aspects.
Course Outline:
1. Industry trends and drivers for copper wire bonding
2. Basic process differences in wire bonding process for gold and copper wires
3. Building blocks for copper wire bonding
4. Wire bonding equipment developments and its influencing factors
5. Copper wire material developments and its influencing factors
6. Capillary developments and its influencing factors
7. Challenges for High density BGA and QFN packages
8. Copper Free Air Ball (FAB) and its impact on First Bond
9. First and Second Bonds challenges and solutions for copper wire bonding
10. Challenges for ultra fine pitch copper wire bonding and its solutions
11. Challenges for copper wire bonding on Low-K and BOAC bondpad structures
12. Looping challenges for copper wire bonding
13. Cu/Al intermetallic compound
14. Interaction between copper wire bonding and mold compound
15. Reliability aspects of copper wire bonded devices
Biography of Instructor:
4. Polymers and nano-composites for electronic and photonic packaging: recent advances
Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance novel No Flow Underfills, Reworkable Underfills for Ball Grid Array (BGA), Chip Scale Packaging (CSP), System in a Package (SIP), Direct Chip Attach (DCA), Flip-Chip (FC), Paper-thin IC and 3D Packaging, Conductive Adhesives (both ICA and ACA), Embedded Passives (high K polymer composites), nano particles and nano-functional materials such as CNTs, graphenes. It is imperative that both material suppliers, formulators and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies.
Course Outline:
1. Fundamental of Polymers and Materials Science and Engineering
2. Materials Needs for Next Generation of Electronic Packaging
3. Novel Nanocomposites for Flip-chip Underfills Applications
4. Recent advances on Nano Lead-free Alloys for High Performance Components Interconnects
5. Low-cost High Performance Lead-free Interconnect Materials and Processes
6. Recent Advances on CNTs as Thermal Interface Materials (TIMs)
7. Lotus Effect Coating for Self-cleaning Applications
8. Fundamental understanding of conductive adhesives
9. Recent advances on conductive adhesives and nano conductive adhesives
10. Application of conductive adhesives
Biography of Instructor:
|
||||||||||||||||||||||||||||||||||||||||||||||||