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Professional Development Courses

Professional Development Course (PDC)
August 16th 2010, AM
EP10-TC1 Quality and Reliability
(Venue: The 1st Conference Room in Tang Cheng Hotel)
Time
Topic
Instructor(s)
8:30—12:30
Advanced Failure Analysis of Semiconductor Packaging
Dr. Goerlich Siegfried
Mr. Xue Ming
EP10—TC2High Density Substrate and SMT
(Venue: The 2nd Conference Room in Tang Cheng Hotel)
8:30—12:30
High Density Interconnect and Substrate Technologies for System-in-Package
Dr.Rickey Lee
 
August 16th 2010, PM
EP10—TC3Cu Wire-bonding
(Venue: The 1st Conference Room in Tang Cheng Hotel)
Time
Topic
Instructor(s)
13:30—17:30
Advanced Cu Wirebonding Technology
Dr. Hong Meng HO
EP10—TC4 Packing Materials and Modeling
(Venue: The 2nd Conference Room in Tang Cheng Hotel)
13:30—17:30
Polymers and nano-composites for electronic and photonic packaging: recent advances
Prof. C.P.Wong
Dr. Daniel Lu
 
 
 To register for PDC, please go to "Conference Registration"
 
Introduction of instructors and courses
 
1.    Advanced Failure Analysis of Semiconductor Packaging
Key FA tools were developed with Semiconductor growth. It is an essential part of the semiconductor technology, as the physical failure root cause and mechanism finding is the key for break through the barrier in technology innovation. Every break-through of FA tool or technique brings forward the semiconductor development. It enables continuously business growth.
The goal for this short course is to address the state-of-the-art of semiconductor failure analysis from various aspects:
1.          60 years history of FA tools and FA role in industry
2.          Advanced FA tools and FA techniques
3.          Broad cross-field transfer know-how in modern FA
4.          Future challenges and Roadmap
The course will be divided into three main sections:
1.          The first section would discuss the FA tools history development and its role for semiconductor development. The fundamental driver for FA would be discussed.
2.          The second section would elaborate the advanced FA based on the latest practical cases from chip level, package level to PCBA level.
3.      The third section would review on the new challenges and the latest semiconductor FA roadmap.
 
Course Outline:
1.      The 60 years development of failure analysis
2.      The role of failure analysis
3.      Advanced FA tools and techniques
A.      Electrical verification and fault localization
B.      Preparation (Chip level, and packages)
C.     Imaging and material characterization
4.      Cross-field transfer know-how in practicing modern failure analysis
A.      Practical cases study (DSO, QFP, VQFN, Stack-die, BGA, Flip-chip, Sip, WLB)
B.      Package reliability risk characterization
5.      Semiconductor Failure Analysis Roadmap
A.      Technology trend
B.      Drivers
C.     Challenges for FA
Biographies of Instructors:
 
Dr. Siegfried Görlich is currently with Infineon Technologies, Germany, working as head of central failure analysis lab. He is involved in design debug, product ramp-up support, latest process development lab support and customer support. He has been with Siemens Central Research and Siemens Semiconductor Group being now Infineon Technologies Germany since 1985. In his 30 years of semiconductor experience, he authored or co-authored more than 100 publications in the field of analytics or failure analysis. Dr. Siegfried Görlich earned a Diploma degree in Physics and a Ph.D. in Electrical Engineering both from the Duisburg University,Germany.
 
 
 
Mr. Xue Ming obtained a degree in radio technology, JaoTong University, Xi An in 1982. He started work in Navigational Aids International, Shanghai in 1982, where he worked 10 years as a product designer / project manager for products in radio receiver, radio transmitter, and wireless remote control system of navigational aids signal. In 1992, he joined Seagate technology international Singapore as a product engineer, and worked 4 years in PCBA process and FA lab. In 1995, he joined Siemens Component, now, Infineon Technologies Singapore as Senior FA engineer. Currently, he is senior manager of the failure analysis lab. In his 15 years semiconductor backend experience, his job involves IC chip and package failure analysis, package reliability characterization, process quality risk management, qualification, customer return and printed circuit board assembly support.
 
2.    High Density Interconnect and Substrate Technologies for  System-in-Package
This course will introduce the cutting-edge information on the most important development and latest research results in applying high density interconnect and substrate technologies to advanced packaging. For professionals active in microelectronic packaging research and development, those who wish to master high density interconnect and substrate technologies, and those who need to choose a cost-effective design and high-yield manufacturing process for their electronic systems, this is a timely summary of progress in all aspects of this technical field. The lecture contents are based on the instructor's books on electronic packaging, his recent research results, and interactions with the packaging and assembly industries. The scope of course covers system-in-package technologies, high density routing, through silicon vias, microvias and build-up layers, silicon interposers and organic substrates, coreless substrates, and special high density interconnect technologies. With the information provided in this lecture, the attendees will acquire a practical understanding in the design, materials, processes, analysis, and reliability issues of high density interconnect and substrate technologies for system-in-package.
 
Course Outline
1.        Overview of system-in-package technologies
2.        Area array interconnection and high density routing
3.        Through silicon vias and silicon interposer
4.        Microvias and build-up layers
5.        Coreless substrates
6.        Special high density interconnect technologies
7.        Applications and case study
8.        Outlook for technology roadmap
 
Biography of Instructor:
 
Dr. Ricky Lee received his PhD degree from Purdue University in 1992. Currently he is Professor of Mechanical Engineering and Director of Center for Advanced Microsystems Packaging at the Hong Kong University of Science & Technology (HKUST). He also serves as Director of HKUST Shenzhen Electronic Materials & Packaging Laboratory. Ricky's research activities cover flip chip technologies and wafer level packaging, through silicon vias and 3D packaging, passive alignment of optical fibers and LED packaging, lead-free soldering and solder joint reliability, computational modeling and stress analysis. He has substantial publications in international journals and conference proceedings. He also co-authored three books (two have been translated into Chinese) and owned several patents. Ricky is very active in international professional societies and has been appointed several leadership positions. He is Fellow of IEEE, ASME, and Institute of Physics. He is also elected IEEE CPMT Distinguished Lecturer and has been giving seminars and workshops worldwide. In addition, Ricky serves as Editor-in-Chief of IEEE Transactions on Components & Packaging Technologies. Due to his contributions in R&D on electronic packaging and assembly, Ricky won IEEE CPMT Electronics Manufacturing Technology Award and ASME EPPD Applied Mechanics Award.
3.    Advanced Cu Wirebonding Technology
Wire bonding is the most dominant form of first-level chip interconnects in microelectronics with gold wire bonding taking the lead for the past few decades. Today, it is evident that the shift from gold to copper wire bonding is genuinely picking up, due to both surge in gold price and recent development in copper wire bonding technology.
The goal for this short course is to address the maturity of copper wire bonding from various aspects:
1.          The technology trends and is it sustainable for the industry to adopt copper wire bonding in replacing gold wire bonding and if so, will gold wire bonding be phasing out.
2.          How do the recent development in equipment, copper wire and capillary help realize copper wire bonding in production implementation.
3.        What are the key process factors to achieve a reliable copper wire bond.
4.          What are the implementation challenges with the downstream process such as interaction with mold compound and its package reliability aspects.
 
Course Outline:
1.      Industry trends and drivers for copper wire bonding
2.      Basic process differences in wire bonding process for gold and copper wires
3.      Building blocks for copper wire bonding
4.      Wire bonding equipment developments and its influencing factors
5.      Copper wire material developments and its influencing factors
6.      Capillary developments and its influencing factors
7.      Challenges for High density BGA and QFN packages
8.      Copper Free Air Ball (FAB) and its impact on First Bond
9.      First and Second Bonds challenges and solutions for copper wire bonding
10. Challenges for ultra fine pitch copper wire bonding and its solutions
11. Challenges for copper wire bonding on Low-K and BOAC bondpad structures
12. Looping challenges for copper wire bonding
13. Cu/Al intermetallic compound
14. Interaction between copper wire bonding and mold compound
15. Reliability aspects of copper wire bonded devices
 
Biography of Instructor:
 
 
 
Dr. Hong Meng HO obtained a degree in Mechanical Engineering in 1989 and a PhD in Mechanical Engineering in 1994, both from the University of Manchester Institute of Science & Technology (UMIST). In 1996, he joined IME, Singapore, as a R&D engineer and then joined Delphi Automotive System Singapore as a senior engineer in 1998. In 2001, he joined IMEC, Belgium, as the Assembly Technology Section Leader, where he started to work on copper wire bonding. In 2003, he joined Kulicke & Soffa Singapore Ball Bonder Division as a staff engineer, responsible for the process development of copper wire bonding. In 2006, he transferred to the K&S Bonding Wire Division as a principal engineer, responsible for the development of new copper wires. Since then, he had developed two new copper wire products that were launched in 2007 and 2008 respectively. In 2009, he joined AceStrella as a consultant and had been conducting workshops on “Advanced Wire Bonding for Semiconductor Manufacturing” in both Malaysia and Thailand. Currently, he is technical director in Semicon Fine Wire Pte Ltd, responsible for the overall research and development of copper bonding wire.
 
 
4. Polymers and nano-composites for electronic and photonic packaging: recent advances
Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance novel No Flow Underfills, Reworkable Underfills for Ball Grid Array (BGA), Chip Scale Packaging (CSP), System in a Package (SIP), Direct Chip Attach (DCA), Flip-Chip (FC), Paper-thin IC and 3D Packaging, Conductive Adhesives (both ICA and ACA), Embedded Passives (high K polymer composites), nano particles and nano-functional materials such as CNTs, graphenes. It is imperative that both material suppliers, formulators and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies.
 
Course Outline:
1.        Fundamental of Polymers and Materials Science and Engineering  
2.        Materials Needs for Next Generation of Electronic Packaging   
3.        Novel Nanocomposites for Flip-chip Underfills Applications         
4.        Recent advances on Nano Lead-free Alloys for High Performance Components Interconnects
5.        Low-cost High Performance Lead-free Interconnect Materials and Processes
6.        Recent Advances on CNTs as Thermal Interface Materials (TIMs)     
7.        Lotus Effect Coating for Self-cleaning Applications       
8.        Fundamental understanding of conductive adhesives         
9.        Recent advances on conductive adhesives and nano conductive adhesives
10.    Application of conductive adhesives
 
Biography of Instructor:
 
Prof. C. P. Wongis a Regents’ Professor and holder of the Charles Smithgall Institute Endowed Chair (one of the two Institute Endowed Chairs at GT) at the School of Materials Science and Engineering at Georgia Institute of technology. He received his B.S. degree from Purdue University, and his Ph.D. degree from the Pennsylvania State University. After his doctoral study, he was awarded a two-year postdoctoral fellowship with Nobel Laureate Professor Henry Taube at Stanford University. He joined AT&T Bell Laboratories as a member of the technical staff and has been involved with the research and development of the polymeric materials (inorganic and organic) for electronic and photonic applications. He became an AT&T Bell Laboratories Fellow (the most prestigious award bestowed by Bell Labs) for his fundamental contributions to low-cost high performance plastic packaging of semiconductors. Since 1996, he is a Professor at the School of Materials Science and Engineering at the Georgia Institute of Technology. He was named a Regents’ Professor (highest rank professor) in July 2000, elected the Class of 1935 Distinguished Professor in 2004 for his outstanding and substained contributions in research, teaching and services, and named holder of the Georgia Tech Institute Endowed chair (one of the two Institute chairs) in 2005.
 
He received many awards, among those, the AT&T Bell Labs Fellow Award in 1992, the IEEE CPMT Society Outstanding Sustained Technical Contributions Award in 1995, the Georgia Tech Sigma Xi Faculty Best Research Paper Award in 1999, Best MS, PhD and Undergraduate Thesis Awards in 2002 and 2004, respectively, the University Press (London) Award of Excellence, the IEEE Third Millennium Medal in 2000, the IEEE EAB Education Award in 2001, the IEEE CPMT Society Exceptional Technical Contributions Award in 2002, elected as holder of the Charles Smthgall Institute Endowed Chair at Georgia Tech in 2005, the Georgia Tech Outstanding PhD Thesis Advisor Award , the IEEE Components, Packaging and Manufacturing Technology Field Award in 2006, the Sigma Xi’s Monie Ferst Award in 2007 and the ASM’s TEEM Award in 2008. He holds over 50 U.S. patents, numerous international patents, has published over 600 technical papers.
 
Dr. Wong is a Fellow of the IEEE and was the president of the IEEE-CPMT Society (1992 &1993). He was elected a member of the National Academy of Engineering in 2000.
 
 
 
 
 
 
Dr. Daniel Lu is the Technical Director of Product Development – Asia Pacific, Henkel Corporation in China. Prior to joining Henkel, he worked for the R&D department of Intel Corp. as a Sr. Scientist and program manager for 7 years. He also had worked for Lucent Technologies, Amoco’s Electronics Materials Division, and the Electronics Materials Group of National Starch and Chemical Company before. He has extensive experience in electronic packaging and materials and processing. He received his MS and PhD degrees on Polymer Science and Engineering from Georgia Institute of Technology in 1996 and 2000, respectively. Dr. Lu received many awards including the IEEE/CPMT Outstanding Young Engineer Award in 2004, the IEEE ECTC best poster paper in 2007, Intel’s most patent filing in 2003-2007, Intel Divisional Recognition Awards in 2002, 2003, and 2007, Intel most patent granting of the year for 2006 and 2007. Dr. Lu has published more than 50 technical papers, wrote chapters for five books, holds 53 US patents, and has more than 20 pending patent applications. He is the editor of the book “Materials for Advanced Packaging” and co-author of the book “Electronically Conductive Adhesives with Nanotechnologies”. He has been serving key roles in organizing international electronic packaging conferences and teaching professional development short courses in these conferences. Dr. Lu is a senior member of IEEE, and an associate editor of IEEE Transactions on Advanced Packaging and Journal of Nanomaterials.
 

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